Integrated circuit (IC) devices are typically tested at two stages during manufacture using production tests. The silicon dies first are tested after fabrication is complete at stations called wafer test or wafer sort. Each wafer is tested, one die at a time, using an array of probes on a probe card that descends onto the bonding pads of a single die. The production tester, a complex machine, applies signals generated by a test program and measures the IC device's test response. In a production test, the only input/output pins that can be accessed are the primary inputs and the primary outputs (e.g., the package pins). A typical IC device can have several hundred primary inputs and therefore each test vector is several hundred bits in length. A test program generally applies hundreds of thousands of different test vectors or patterns at a frequency of several megahertz over several hundred milliseconds during the test session. Those IC devices that fail are then rejected. A second test is then performed after the die has been packaged. Again, those IC devices that fail are rejected.
Fabrication of an IC device is a complex process and problems in this process can introduce a defect that causes a fault in the circuit. Any problem during fabrication can prevent a transistor from operating properly and can break or join interconnections. Two common types of defects occur in metallization: either underetching the metal (a short occurs) or overetching the metal (an open circuit occurs). Defects can also occur in processes that are performed after the fabrication is complete, e.g., testing of the wafer, cutting the die from the wafer, mounting the die in a package, etc.
To test the IC device, a series of test vectors (patterns) need to be devised that test for particular faults. Fault simulation is used after logic simulation to determine the manner in which an IC device responds when a deliberately introduced fault is added at a particular point in a circuit netlist. These faults are typically stuck-at faults, e.g., stuck-at zero (0) or stuck-at one (1) where the node is always a logical 0 or a logical 1, respectively, during circuit simulation. During fault simulation, the output of the faulty netlist is compared to the output of a good netlist without introduced faults. If the outputs are different, then the selected fault is said to be a "detected fault" with respect to the netlist. The extent to which faults can be detected by a series of test vectors (e.g., a test program) for a given netlist defines the fault coverage of the test program. If a particular test program does not deliver adequate fault coverage, it is modified and fault simulation is repeated.
Automatic test pattern generation (ATPG) processes are used to devise test patterns using complex computer implemented processes. The goal of ATPG processes applicable to sequential circuits is to generate test vectors to test the maximum number of stuck-at faults in the circuit (e.g., in the netlist). See, as background, the reference by M. Abramovici, M. A. Breuer, and A. D. Friedman, entitled "Digital Systems Testing and Testable Design," available from Computer Science Press, 1990. To do so, the ATPG process for sequential circuits uses processes taken from ATPG processes that are dedicated for combinatorial circuits and applies them using a model called "Iterative Array Representation of Sequential Circuits" (IAR) as described in the Abramovici reference. See, also as background, the reference by H. Fujiwara and T. Shimon, entitled "On the Acceleration of Test Generation Algorithms," from IEEE Transaction on Computers, Volume C-32, N. 12, pp. 1137-1144, December 1983. In the IAR representation, the circuit is virtually replicated in time and every replication represents a stable state of the circuit. Transitions in between the frames (a frame denotes a single representation of the circuit) represent a clock signal toggling. The AIR representation was originally used for single clock circuits.
However, other approaches (e.g., Sunrise Test Systems reference Manual Version 1.2a/August 1993) keep the original IAR representation and increase the complexity of the sequential modeling to handle ATPG in multiple clock circuits. In this approach, additional circuitry is introduced to the sequential modeling in proportion to the number of additional clocks that are found the multiple clock circuit. Since the sequential circuit model is altered to account for the multiple clocks, this prior art approach is called a "dynamic" sequential circuit model. The additional circuitry increases geometrically as multiple clocks are added and as additional sequential circuits are used within netlists. This additional circuitry of the dynamic sequential circuit model increases the time and computer resources required to perform ATPG for netlists that contain sequential circuits and have multiple clocks.
Accordingly, what is needed is an efficient method and system for performing ATPG on netlists having sequential circuits and multiple clock signals. A further need exists for a method and system for performing ATPG on netlists having sequential circuits and multiple clock signals that does not utilize a dynamic model of the sequential circuit. Still another need exists for a method and system for performing ATPG on netlists having sequential circuits and multiple clock signals that uses the same model for sequential circuits as is used in single clock models. The present invention provides the above advantageous features and others not specifically recited above but clear within discussions of the present invention herein.